en:lib:mdl:mdl-h-cediginp-010

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en:lib:mdl:mdl-h-cediginp-010 [2015/07/16 09:05] – documentazioneen:lib:mdl:mdl-h-cediginp-010 [2019/08/29 17:01] (current) – external edit 127.0.0.1
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 +|Type of polarisation|  PNP  | 
 +|Min. acquisition time (hardware)|  3ms  | 
 +|Isolation|  1000Vrms  | 
 +|Rated operating voltage|  24Vdc  | 
 +|Voltage of logic state 0|  0-2 V  | 
 +|Voltage of logic state 1|  10.5 - 26.5 V  | 
 +|Internal voltage drop|  5V  | 
 +|Input resistance (Ri)|  2700Ω  | 
 +|Sink current|2mA ÷ 8mA[(**CAUTION: If the device connected to the inputs needs a higher minimum current, inputs may not work properly.**)]  | 
 +~~REFNOTES~~ 
 +{{schemi:sch_in_standard_01.png?nolink&400|Internal diagram of standard digital input.}}