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| en:lib:mdl:mdl-h-cecount-010 [2015/05/04 17:04] – documentazione | en:lib:mdl:mdl-h-cecount-010 [2024/01/31 08:32] (current) – documentazione | ||
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| + | <WRAP center round tip 60%> | ||
| + | The values given in the table refer to input signals A, B and Z.\\ The max. frequency given in the table refers to A and B phase signals with a DutyCycle = 50%\\ With count frequencies over 50KHz the use of Line-Driver type encoders is recommended. | ||
| + | </ | ||
| + | === Push-Pull === | ||
| + | |Type of polarisation| | ||
| + | |Max frequency| | ||
| + | |Min. acquisition time| 5µs | | ||
| + | |Insulation| | ||
| + | |Rated operating voltage| | ||
| + | |Voltage of logic status 0| 0 - 2 V | | ||
| + | |Voltage of logic status 1| 10.5 - 26.5 V | | ||
| + | |Internal voltage drop| 1.2V | | ||
| + | |Input resistance| | ||
| + | === Line-Driver === | ||
| + | |Type of polarisation| | ||
| + | |Max. frequency| | ||
| + | |Min. acquisition time| 5µs | | ||
| + | |Insulation| | ||
| + | |Rated operating voltage (PHx+ ? PHx-)| | ||
| + | |Voltage of logic status 0 (PHx+ ? PHx-)| | ||
| + | |Voltage of logic status 1 (PHx+ ? PHx-)| | ||
| + | |Internal voltage drop| 1.2V | | ||
| + | |Input restistance| | ||
| + | |||
| + | {{schemi: | ||